The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a structure and method for forming semiconductor wiring levels using atomic layer deposition (ALD).
In the semiconductor industry, there is a continuing trend toward higher device densities by scaling down the device dimensions on semiconductor wafers (e.g., at submicron levels). In order to accomplish such high device packing density, smaller and smaller feature sizes are required. These feature sizes may include, for example, the width and spacing of interconnecting conductive lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various device structures.
The requirement of small features (and close spacing between adjacent features) in turn requires high-resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. More specifically, it is a technique used for integrated circuit fabrication in which a silicon slice (i.e., the wafer) is coated uniformly with a radiation-sensitive film (i.e., the resist), and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template (i.e., the photomask) for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photomask causes a chemical transformation in the exposed areas of the coating, thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. However, such lithography is not without limitations. Patterning features having dimensions of about 100 nanometers or less with acceptable resolution is difficult at best, and almost impossible in certain circumstances. At these dimensions, the tolerances become very difficult to control. Patterning conductive features with small dimensions, such as conductive metal lines for example, is required in order to participate in the continuing trend toward higher device densities. Accordingly, it has become desirable to obtain alternative methods of scaling conductive wiring in order to provide enhanced resolution, tolerance control, and improved critical dimension values.